Catalog > 204B Controller (JESD204B)
Multilane JESD204B TX & Rx controller with support for deterministic latency.
Soft IP- Silicon Proven
SILABTECH JESD204B controller IP is designed for enhancing the off-chip connectivity with a fully compliant JESD204B interface. The programmable stream interface, APB interface and DFT structures enable easy integration and validation at SoC level.
The controller enables deterministic latency using the system generated SYSREF signal. The unique latency control logic with register programmed values, allows the cancellation of any board, connector or chip delays, thereby enabling true real-time data transfers. The efficient lane alignment algorithm enables lane alignment and latency equalization in the JESD204B receiver.
The built-in interrupt controller enables the SW to track any Data transfer or protocol issues. The controller IP supports all the standard link test modes. The DFT features enable easy integration at SoC level.
The JESD204B controller will enable the following applications:
• Interfacing a baseband SoC with external high-performance ADC or DAC (1+ GSPS; 12+ ENOB)
• Point-to-point interconnection to external RF chips
• Interfacing to FPGAs from all types