Catalog > CWdc02 - LZRW3 Lossless Data Decompressor
The LZRW3 Lossless Data Decompressor (CWdc02) is an IP core for data decompression that uses the Lempel–Ziv Ross Williams algorithm. This algorithm is a variant of the LZ77 algorithm, targeting hardware implementations. The CWdc02 IP core is designed to operate in combination with the LZRW3 Lossless Data Compressor, CWdc01
The operation of the core is initialized when the start signal is asserted. In the next clock cycle, the core is ready to accept one byte per clock cycle. Each input byte must be validated using the data_in_valid signal. The size of the input block (data_in_size) must be provided after the assertion of the start signal and while the done signal is deasserted.
The initial latency depends on the input data. The average latency is 5 clock cycles to produce the first output byte.
The end of decompression is signaled by the done output signal. The size of the decompressed data (data_out_size) is also available at that moment.
Whenever the data_out_valid signal is asserted, the user must capture the output data (data_out). Each output byte is available during one single clock cycle.
As soon as the done signal is asserted, a new start can be initiated. However, the internal memories hold the results of the last decompression, which impacts future decompression results.
The perform a correct decompression, the contents of the internal memories must be identical in the compressor and decompressor. To keep these memories synchronized, both IP cores (CWdc01 and CWdc02) have a signal (hash_init) that restores the default status of the internal memories. In practice, whenever the compressor perform this initialization, the decompressor must also perform the initialization. This action takes 512 clock cycles to complete.
- Lossless data decompression using the Lempel–Ziv Ross Williams algorithm named “LZRW3”
- Maximum output block size: 8 kBytes
- Maximum throughput (bytes/s): 0.888 x clock frequency
- Seamless integration with the LZRW3 data compressor (CWdc01)
- Average latency of 5 clock cycles (depends on input data)
- Reinitialization of the hash table is controlled by the user (useful to synchronize the compressor and decompressor)
- FPGA netlist or RTL
- Implementation constraints