Catalog > CWdc01 - LZRW3 Lossless Data Compressor
The LZRW3 Lossless Data Compressor (CWdc01) is an IP core for data compression that uses the Lempel–Ziv Ross Williams algorithm. This algorithm is a variant of the LZ77 algorithm, targeting hardware implementations. This IP core is designed to operate in combination with the LZRW3 Data Decompressor, CWdc02.
The operation of the core is initialized when the start signal is asserted. Synchronously with this activation, the core reads the size of the input block (data_in_size). Subsequently, it waits for input data, being ready to accept one byte per clock cycle. Each input byte must be validated using the data_in_valid signal.
The initial latency is not fixed. The core requires from 16 to 32 bytes to produce the first output byte, depending on the input data.
The end of compression is signaled by the done output signal. At this moment, the size of the compressed data (data_out_size) is also available in the output interface.
Whenever the data_out_valid signal is asserted, the user must capture the output data (data_out). Each output byte is available during one single clock cycle.
As soon as the done signal is asserted, a new start can be initiated. However, the internal memories hold the results of the last compression, which affects the compression results. Nevertheless, if the compressor and the decompressor are not reinitialized between consecutive blocks, then the process of compressing, followed by decompression, still produces the correct result.
In noisy environments, the transmission of the compressed data can be corrupted. To recover from these errors, it is necessary to reinitialize the compressor and decompressor at the same time. This initialization is performed using the signal hash_init, which must be applied to the same block of data in both modules. This action takes 512 clock cycles to complete, so, to preserve a high throughput, it should not be done frequently.
- Lossless data compression using the Lempel–Ziv Ross Williams algorithm named “LZRW3”
- Input interface accepts one byte per clock cycle (no idle states)
- Maximum input block size: 8 kBytes
- Average compression ratio: 55%
- Maximum compression ratio: 87.9%
- Latency ranges from 16 to 32 clock cycles (depends on input data)
- Reinitialization of the hash table is controlled by the user (useful to synchronize the compressor and decompressor)
- FPGA netlist or RTL
- Implementation constraints