Catalog > CWda14 - SPDIF-Rx-Pro : Configurable SPDIF-AES3 Receiver
The SPDIF-Rx-Pro (CWda14) is a digital audio receiver IP core supporting the SPDIF and AES3 and IEC60958 standards and also adds hardware support for the IEC61937 and SMPTE 337M standards for non-PCM (compressed) audio.
This purely digital clock and data recovery method dispenses the classical analog PLL at the input reducing the receiver cost.
The Modular structure of the CWda14 allows enhanced functionality for specific applications by using the optional Add-on-Modules (AOM).
- Supports the SPDIF (IEC60958) and AES3 standards for stereo PCM audio transmission
- Supports the IEC61937, SMPTE 337M standards for non-PCM audio transmission (Dolby Digital, AAC, DTS, MPEG, etc)
- Digitally de-jitters recovered clock and outputs a good quality audio retransmission clock
- Automatic removal of stuffing bits in non-PCM mode
- Average 0.6 sample periods (0.6/Fs) lock time
- System clock (fclk) minimum required frequency Ffclk = 420*Fs for Fs = 96kHz or lower, or Ffclk = 640*Fs for Fs = 192 kHz
- Optional separate interfaces for data and control
- Optional channel Status and User bits memory mapped buffers
- Programmable FIFO level trigger
- Configurable endianness for both control and data interfaces
- Measures and reports input signal sample rate
- Optional AMBA® AHB master interface with embedded DMA controller and memory ping-pong buffers
- I2S output port
- Verilog source code or FPGA netlist
- RTL testbench
- Synthesis constraints
- Evaluation board (optional)