Catalog > CWda73 - AAC-LC And HE-AAC Audio Decoder
The AAC-LC and HE-AAC Audio Decoder (CWda73) is an audio IP core for decoding up to 6 audio channels in real-time.
This core contains the AAC-LC/HE-AAC v1 decoder software and the Coreworks processor based hardware audio engine platform (CWda3111).
The software is compiled into an image file (.bin) which can be automatically boot-loaded through one of the control interfaces (parallel AMBA APB or serial SPI) and run on the audio engine platform with simple parameters setting.
The program can be configured, controlled and monitored by means of a configuration, control, and status register file, accessed by the control interfaces.
The audio input and output interfaces uses a native parallel interface. Other standard audio interfaces, such as I2S/TDM and SPDIF are also available.
The interface to the external memory can be one of the following: AMBA AXI (for ASICs or Xilinx FPGAs), Avalon (for Altera FPGAs) or MIG (for Xilinx FPGAs).
The CWda3111 platform is an instance of the generic CWdaXYZ Audio Engine Platform. Other platforms are available for a different number of audio channels (from 2 channels, up to 32 channels). Please contact us to select the best solution for your requirements.
- MPEG2/4 AAC LC, HE-AAC v1, software employed Fraunhofer IIS high quality software which supports ISO/IEC 13818-7, ISO/IEC 14496-3 and Japanese ARIB standard
- Supported channel modes: mono, dual mono, stereo (2.0), 2.1, 3.0, 3.1, 4.0, 5.0, and 5.1
- Supported sampling rates: 8, 16, 22.05, 32, 44, 44.1 and 48 kHz
- Supports multiple audio streams – limited to 6 audio channels in total (e.g. 3 stereo streams)
- Maximum 16-bit output audio resolution
- Requires 6.9 MB of external memory
- Configurable output latency useful to synchronize with other sources (e.g. video)
- Minimum latency: 1 frame assuming burst data input
- Software interface protocol for control, configuration and monitoring
- Parameter change while muting or repeating one frame
- Supported transport types: raw, ADTS, ADIF, LATM, and LOAS
- Real time operation @80 MHz for worst-case settings. Results for other settings can be provided upon request
- Program binary
- Software manual
- Netlist or RTL
- Implementation constraints
- Hardware datasheet
- Simulation environment or evaluation board (optional)